In a high speed source-synchronous semiconductor memory system, such as a double data rate synchronous dynamic random access memory (“DDR SDRAM”), data is transferred to or from other devices, where the data is synchronized with a clock signal (e.g., a reference clock or an external clock signal). The high speed source-synchronous semiconductor memory device performs an input or output operation in synchronization with not only a rising edge, but also a falling edge of the clock signal. Typically, in a system or a circuit including a semiconductor memory, the clock signal is used as a reference clock signal for adjusting operation timing to guarantee stable data access and data transfer without error. For stable data access and data transfer, the data transfer should occur with respect to the clock edges in such a way that the memory or physical layer (“PHY”) can recover the data send synchronized to each clock edge. A delay locked loop (“DLL”) can generate internal clock signals for the system based upon the reference clock signal by compensating for clock skew occurring in the data path and adding phase delays to the reference clock signal. The data path has a predetermined delay amount estimated from the clock skew, where the data or the clock signal passes through the semiconductor memory device. The generated internal clock signals can then be used for synchronizing data input/output.
DLLs can be used to supply these internal clock signals based on the reference clock signal. Typically, DLLs are based on a variable multi-stage delay line, in which the delay is controlled by a phase/frequency detector which compares the signal at the end of the delay line with the reference clock signal. It is appreciated that DLLs may also comprise of other components, including a charge pump and filter to name a couple. Taps between stages in the delay line provide multiple copies of the reference signal with various phase shifts so as to subdivide the clock period into different phase delay levels.
A DLL usually provides delays in steps up to a full clock cycle delay for the input signal. Typically, the DLL can have eight delay segments (also referred to as octants) or any other number of segments, e.g., 4 or 16 stages, that are connected in series to provide total delay up to one clock period. Each delay element of the DLLs can provide a delay of around ⅛th of a full clock cycle (assuming it has 8-stages; if N-stages delay, then each can provide 1/N of a period). In particular, a DDR system's data strobe and data bits require alignment across the system. In order to do so, the DDR system typically implements a master-slave DLL network, where a master DLL sets the required delay times and can drive one or more slave delay lines for delaying signals, including a DQS strobe. Thus, the master DLL can force a specific delay onto the slave DLLs.
FIG. 1 illustrates a prior art master-slave delayed locked loop system. A master-slave delayed locked loop system of the prior art comprises a master delay locked loop (“MDLL”) regulator 10, an MDLL 9, a slave delay locked loop (“SDLL”) 32, a phase interpolator (“PI”) array 34, and a SDLL regulator 36. The MDLL regulator 10 provides a stable and lower noise supply to the components used in the MDLL 9. The MDLL 9 comprises flip-flop (“FF”) 12, FF 14, a delay logic 16, an AND gate 18, current sources 20 and 26, switch transistors 22 and 24, a filter capacitor 28, and master delay elements 30. The MDLL 9 uses a voltage control to adjust the delay elements of the master delay elements 30 for aligning signal CK0 with CK360. CK0 is usually a delayed version of the clock in signal CKIN_MDLL. The master delay elements 30 include delay elements as well as any logic or circuitry for the delay elements to function.
The MDLL 9 can generate slave bias currents for controlling one or more slave DLLs (e.g., the SDLL 32) based on the adjustments made to the master delay elements 30. The controlled SDLL 32 replicates the desired calibrations of the master delay elements 30 and applies it to a clock in signal CKIN_SDLL to generate its output clocks that have phase shifts from 0 degrees to 360 degrees. The phase shifted clock signals are inputted to the PI array 34 for generating clocks with much finer shifts in phase than can be provided by the delay lines themselves to use in clocking read and write commands and data. The SDLL regulator 36 can be used to provide information from the PI array 34 to the SDLL 32. The SDLL regulator 36 provides a stable supply to the components of the SDLL 32.
Due to the design and/or process, voltage and temperature (“PVT”) fluctuations between the MDLL 9 and SDLL 32, the SDLL 32 may not operate identically as the MDLL 9. Thus the delay provided by the MDLL 9 is not exactly replicated in the SDLL 32, there will be differences in the set delays. For instance in DDR systems, data strobe and data bits need to be aligned across the system spanning several 100's μms such that the eye is maximized. There is usually one MDLL (or master phase locked loop) that generates the bias voltages or currents that determine the delay. This control bias is then distributed to various data macros where the local slave delay lines are used to align the strobe to the data byte.
DDR physical layer (“PHY”) systems can easily span several 100's μm. Hence, the delay generated in the MDLL is substantially different from delay in slave DLLs due to PVT variations across these distances. These differences in delays will reduce the available valid timing eye for aligning data and strobes. Usually data strobe is aligned to data by delaying it by 90°-180° based on settings from the MDLL. At certain speeds, this delay difference can reduce the eye and be a significant issue, which can lead to read failures, write failures, and other failures.
Therefore, it is desirable to provide new circuits, methods, and systems for a clock alignment scheme to account for PVT variations in a slave DLL.